The present invention relates generally to computer systems and, more particularly, to methods and apparatus for interfacing multiple I/O subsystem buses to a common computer system bus.
Computer systems have traditionally included a central processing unit or CPU, data storage devices including a main memory which is used by the CPU for performance of its operations and a system bus which interconnects the CPU to the main memory and any other data storage devices. In addition, I/O devices are connected to the system via the bus. The bus thus serves as a communications link among the various devices making up a system by carrying clock and other command signals and data signals among the devices.
To improve the operation of computer systems for performing more and more instructions in less and less time, computer systems have evolved to systems which include multiple computers and/or multiple system buses. While substantial improvements have been made, operation of these computer systems is still limited by the system bus or buses which ultimately are overcome by the massive amounts of data and control information which must be passed between units coupled to the bus.
To expand the capacity of the system bus or buses, subsystem I/O buses have been added to computer systems. A subsystem I/O bus is typically coupled to the system bus or buses to connect additional devices or agents to the computer system such that these additional resources can be used by the computer system and thereby expand the processing capabilities of the system. The addition of a subsystem I/O bus is advantageous since it presents only one load for the system bus or buses yet provides system access to a number of agents. If the agents are directly coupled to the computer system, they load the bus with a load per device, such as eight or sixteen bus loads, as opposed to the single bus load presented by the subsystem I/O bus.
It is desirable to further expand the capacity of a computer system by the addition of multiple subsystem I/O buses each of which presents only one system bus load but expands the resources available by a number substantially greater than one. Unfortunately, available subsystem buses include hardware which is not compatible in terms of memory space and input/output (I/O) space allocation within a computer system which includes more than one or multiple subsystem I/O buses. Further, known subsystem I/O buses include hardware which fixes certain addresses associated with the subsystem buses.
Accordingly there is a need for methods and apparatus for interfacing multiple subsystem I/O buses to the system bus or buses of a computer system.